Flutterby™! : ADSL training

Light reading ADSL TUTORIAL: Extracted from the Introduction and Chapter 1 of A G.hs Handshaking Protocol Analyzer For ADSL, a Master’s Project by Matthew J. Langlois, May 2002.

With reference to Figure 9, the Cell TC block handles all ATM specific requirements, including header error control (HEC) generation, idle cell insertion, cell payload scrambling, bit timing and ordering, cell delineation, and HEC verification. The ATM Cell TC block essentially handles the conversion of ATM data to ADSL bearer channel data. Again, in ADSL systems transporting STM data, the ATM Cell TC block is not utilized. Following the ATM Cell TC block, data is routed, through bearer channels, to the Mux/Sync Control block. The Mux/Sync Control block synchronizes data to the 4kHz ADSL data frame rate and multiplexes data into the fast and/or interleaved data buffers.

Mostly because I was unhappy with the class description of interleaving in ADSL and ADSL2+ and wanted to understand it. Looks like interleaving does decrease latency and increase the circuit's ability to maintain sync in noisy situations, but it increases throughput. If I'm reading this paper right, massively. Need to test in the real world...